Architectural Study and Simulation of RISC and CISC Architectures"

Abstract

The microprocessor unit (MPU) or central processing unit (CPU) constitutes the fundamental component that determines the performance of computing systems, as it executes instructions and coordinates the operation of system components according to a defined architecture. Advances in integrated circuit technologies have led to increasingly complex designs, making the evaluation of instruction set architectures (ISA) essential for understanding processor operational characteristics. Two major paradigms have emerged: Complex Instruction Set Computer (CISC), which provides multifunctional instructions within a complex structure that allows high-level operations to be executed with a single instruction but requires more intricate design; and Reduced Instruction Set Computer (RISC), which relies on a limited set of simple instructions, typically executed in a single clock cycle, thereby enhancing efficiency and speed while simplifying design. This study employs MATLAB to simulate selected instructions in both RISC and CISC architectures, serving as a practical example of distinctive instructions in each paradigm. The results were compared in terms of instruction count, clock cycles, code size, and execution efficiency. The simulation outcomes demonstrated the superiority of RISC architecture over CISC in terms of execution time and overall efficiency, despite requiring a larger number of instructions and greater program size. Conversely, the CISC architecture relied on a single complex instruction that reduced program size but resulted in longer execution time and lower efficiency. The study recommends expanding the scope of simulation by incorporating additional instructions such as addition, subtraction, and branching to assess architectural behavior under more complex conditions. Furthermore, integrating additional metrics such as power consumption would provide a more comprehensive perspective on performance.